The present invention relates generally to liquid crystal displays (LCDs), and deals more specifically with an LCD which has sensitive regions protected by insulating and/or passivation layers.
Active-matrix-type LCDs use thin-film transistors (TFTs) as switching elements. An active-matrix-type LCD includes a TFT array substrate in which scan signal lines and display signal lines are arranged in the form of matrix. TFTs are arranged on intersection points thereof, and a color filter substrate is located at a predetermined distance from the TFT array substrate. A liquid crystal material is filled between the TFT array substrate and the color filter substrate. The TFTs supply voltages to the liquid crystal material, and cause luminance due to electro-optic effect of the liquid crystal.
As the number of pixels increase to improve definition of an active-matrix-type LCD, the following problems have arisen. The number of display signal lines and scan signal lines have significantly increased along with the number of pixels and the number of driver ICs. This has increased cost and complexity. Also, an electrode pitch at which a driver IC and a TFT array substrate are connected has narrowed, whereby the connections have become difficult and the yield has been reduced.
Many solutions have been proposed to reduce the number of circuit components. For example, an electric potential can be supplied from one display signal line to two or more adjacent pixels in a row. The signal for each pixel is provided in a time-division multiplexed manner to reduce the number of driver ICs. See U.S. patent application Ser. No. 10/317,503 filed Dec. 12, 2002 by K. Abe, E. Kanzaki and M. Kodate, Japanese Unexamined Patent Publications No. Hei 6(1994)-138851, No. Hei 6(1994)-148680, No. Hei 11(1999)-2837, No. Hei 5(1993)-265045, No. Hei 5(1993)-188395, and No. Hei 5(1993)-303114, for example.
A TFT array substrate with the multiplexed IC drivers can be manufactured using a photo engraving process (hereinafter referred to as photolithography). A TFT array substrate can be made in a seven step photo lithographic process using conventional technology. Attempts have been made to reduce the number of photo lithographic steps to five, but problems have arisen. In the five step process, a portion of the liquid crystal layer or an alignment layer electrically connected to a scan signal line or to a gate electrode is exposed. This phenomenon is described in detail below, and is hereinafter referred to as “gate potential” exposure. This exposure adversely affects image characteristics.
This problem is illustrated by FIGS. 17–20, in which a multiplexed pixel display device 22 was manufactured using a conventional, five step (or “reduced”) photolithographic-step process. FIG. 17 is an equivalent circuit diagram showing the multiplex pixel display device 22. Pixel electrodes A100 and B100 are adjacent to each other across a display signal line Dm. There are three switching TFTs—M1, M2 and M3 arranged as follows. Source and drain electrodes of TFT M1 are respectively connected to the display signal line Dm and the pixel electrode A100. A gate electrode of TFT M1 is connected to a source electrode of TFT M2. In the illustrated example, a TFT source terminal is connected to a display signal line Dm and a TFT drain terminal is connected to a pixel electrode. However, the drain and source terminals can also be reversed with analogous operation. Therefore, in the following description, both the source and drain terminals will be referred to as a source/drain terminal or electrode.
The source/drain electrodes of TFT M2 are respectively connected to the gate electrode of TFT M1 and a scan signal line Gn+2. Therefore, the gate electrode of TFT M1 is connected to the scan signal line Gn+2 through the second TFT M2. A gate electrode of TFT M2 is connected to a scan signal line Gn+1. Accordingly, only for a period when the two adjacent scan signal lines Gn+1 and Gn+2 are simultaneously at a selection potential (hereinafter referred to as “selected”), TFT M1 is turned on. Thereby an electric potential of the display signal line Dm is supplied to the pixel electrode A100.
Source/drain electrodes of TFT M3 are respectively connected to the display signal line Dm and the pixel electrode B100. A gate electrode of TFT M3 is connected to the scan signal line Gn+1. Accordingly, when the scan signal line Gn+1 is selected, TFT M3 is turned on. Thereby the electric potential of the display signal line Dm is supplied to the pixel electrode B100.
FIG. 18 is a plan view schematically illustrating a semiconductor configuration in the vicinity of pixel electrodes C100 and D100 of the multiplex pixel display device 22 shown in FIG. 17. As described above, the multiplexed pixel display device 22 is manufactured using photolithography. In FIG. 18, the same shade is applied in layers prepared through the same photo lithographic step. The shade also shows the order of process step. A lighter shade shows a preceding step. It can be seen that the scan signal lines Gn+1 and Gn+2, for example, are formed prior to the display signal line Dm.
In FIG. 18, TFT M1 has the source/drain electrode 51 which is connected to the pixel electrode A100, the source/drain electrode 61 which is connected to the display signal line Dm, and the gate electrode 71. TFT M2 has the source/drain electrode 52 which is connected to the gate electrode 71 of TFT M1 through a connector 81, the source/drain electrode 62 which is connected to the scan signal line Gn+2, and the gate electrode 72, which is part of the scan signal line Gn+1. A branched line 83 is connected to the scan signal line Gn+2 through a connector 82. Part of the branched line 83 constitutes the source/drain electrode 62.
FIG. 19 is a cross-sectional view taken along the line Z—Z in FIG. 18. Note that a scale of FIG. 19 is different than that of FIG. 18. The scan signal lines Gn+1 and Gn+2 and the gate electrode 71 are formed on a glass substrate 95. A gate insulating film 94, which covers the scan signal lines Gn+1 (gate electrode 72) and Gn+2, and the gate electrode 71, is formed on the glass substrate 95. On the gate insulating film 94, semiconductor layers 931 and 932 are formed at portions relevant to TFTs M1 and M2. The source/drain electrodes 51 and 61 are formed on the semiconductor layer 931 and constitute TFT M1 together with a channel protection film 96. In addition, the source/drain electrodes 52 and 62 are formed on the semiconductor layer 932 and constitute TFT M2 together with a channel protection film 96. Furthermore, a passivation film 91 is stacked on these films. On the gate electrode 71, a contact hole 97, penetrating the gate insulating film 94 and the passivation film 91, is formed. Meanwhile, on the source/drain electrode 52, a contact hole 98 penetrating the passivation film 91 is formed. The connector 81 enters into the contact holes 97 and 98, whereby the source/drain electrode 52 and the gate electrode 71 are electrically connected. A contact hole 100 penetrating the gate insulating film 94 and the passivation film 91 is formed on scan signal line Gn+2. Meanwhile, a contact hole 99 penetrating the passivation film 91 is formed on the source/drain electrode 62. The connector 82 enters into the contact holes 99 and 100, whereby the source/drain electrode 62 and the scan signal line Gn+2 are electrically connected. The passivation film 91 is not formed on the connectors 81 and 82. Therefore, the gate electrode 71 and the scan signal line Gn+2 are exposed outside through the connectors 81 and 82, respectively. Although not shown in FIG. 19, an alignment film is generally formed on the passivation film 91, and moreover, a liquid crystal layer is provided on the alignment film. Accordingly, the gate electrode 71 and the scan signal line Gn+2 are in electrical contact with the alignment film. In such a structure, when an electric potential (gate potential) is supplied to the gate electrode 71 and the scan signal line Gn+2, electric charges are endlessly supplied to the alignment film in a region where the connectors 81 and 82 are in contact with the alignment film. Accordingly, impurity ions present in the liquid crystal layer concentrate in this region, whereby a voltage drop or an electric charge retention failure occurs and this causes deterioration in image quality.
FIGS. 20(a) to 20(e) illustrate a process in which the display device 22 is manufactured by the conventional five step/reduced photo lithographic process.
First, a metal film to form the scan signal lines Gn+1 (gate electrode 72) and Gn+2 is formed on the glass substrate 95. After the metal film is formed, the gate electrode 71 and the scan signal lines Gn+1 (gate electrode 72) and Gn+2 are patterned by photolithography as shown in FIG. 20(a).
Next, the gate insulating film 94 and a semiconductor layer 93 are formed on the glass substrate 95 on which the gate electrode 71 and the scan signal lines Gn+1 (gate electrode 72) and Gn+2 are formed. Moreover, a film to form the channel protection films 96 is formed on the semiconductor layer 93. Thereafter, as shown in FIG. 20(b), the channel protection films 96 are patterned on the semiconductor layer 93 by photolithography.
Next, a metal film to form the source/drain electrodes 51, 61, 52, and 62 and the branched line 83 is formed. After this metal film is formed, the source/drain electrodes 51, 61, 52, and 62, the branched line 83, and the semiconductor layers 931 and 932 are patterned by photolithography as shown in FIG. 20(c).
Next, the passivation films 91 is formed as follows. The passivation film 91 is patterned by photolithography as shown in FIG. 20(d). At the time of this patterning, the contact holes 97, 98, 99, and 100 are formed.
After the passivation film 91 is formed, a film, for example, an indium tin oxide (ITO) film, to form the pixel electrodes is formed by sputtering. The connectors 81 and 82 are also prepared using this ITO film. After the ITO film is formed, the connectors 81 and 82 are patterned by photolithography as shown in FIG. 20(e).
In the display device 22, there are two portions where the gate potential exposure occurs: a connecting portion between the first and second TFTs M1 and M2 and a connecting portion between the branched line 83 and the scan signal line Gn+2. These two portions and gate potential exposures occur at every pixel electrode. The gate electrode 71 of TFT M1 and the source/drain electrode 52 of TFT M2 are connected through the connector 81. Moreover, the branched line 83 and the scan signal line Gn+2 are connected through the connector 82.
The reason why connection using the connectors 81 and 82 is required is that the gate electrode 71 and the scan signal line Gn+2 are respectively formed through photo lithographic steps different from those of the source/drain electrode 52 and the branched line 83 and then the contact holes are formed. For example, if the connector 81 is formed prior to the passivation film 91, the gate potential exposure can be prevented, but there is no room to insert the connector 81 prior to the passivation film 91 in a case of the five-photolithographic-step process described with reference to FIGS. 20A to 20E.
An object of the present invention is to provide a technology which prevents portions electrically connected to a scan signal line or a gate electrode from being exposed on a liquid crystal layer or on an alignment layer in a multiplex pixel display device even in a case of use of a reduced-photolithographic-step process.
Another object of the present invention is to provide a liquid crystal display device which use this technology.